The present invention relates to a read circuit of a non-volatile semiconductor memory.
1. Types of Fast Random Accessible Nonvolatile Semiconductor Memories
As fast random accessible nonvolatile semiconductor memories, EEPROM, NOR cell type flash memory, and the like are known. In recent years, new types of memories based on a NAND cell type flash memory have been devised as a memory having a fast random access characteristic in parallel with these memories. One of such memories is a so-called “3Tr-NAND.”
The 3Tr-NAND is a memory which has each cell unit composed of three transistors, i.e., one memory cell and two select transistors sandwiching the memory cell, and has the following characteristics as compared with the EEPROM or flash memory:
(1) ability of fast read in units of 16 bits (=word);
(2) a small erasure unit of 32 words;
(3) ability of performing a read operation at low power consumption; and
(4) relatively small memory cell size.
Specifically, the 3Tr-NAND is, for example, smaller in memory cell size as compared with the EEPROM, and can therefore accomplish a reduction in chip size, a reduction in manufacturing cost, and the like. Also, the 3Tr-NAND requires lower power consumption and provides a smaller erasure unit as compared with a NOR cell type flash memory (for further details on 3Tr-NAND, see for example Japanese Patent Application No. 11-10676 (filed on Jan. 19, 1999)).
2. Read Circuit of NOR Cell Type Flash Memory
As to an access time upon reading, the 3Tr-NAND is equivalent to the NOR cell type flash memory. Specifically, the two memories require approximately 100 nsec. As such, the following description will be made on a read circuit of a NOR cell type flash memory as a conventional read circuit.
Also, for facilitating the understanding of the following description, definitions are made as follows beforehand about data in a memory cell. Specifically, it is assumed that a memory cell with a positive threshold voltage is a memory cell which stores “0” data (or “0”-programming cell), and a memory cell with a negative threshold voltage is a memory cell which stores “1” data (or “1”-programming cell or a erasure cell).
It should be noted that the threshold voltage of a memory cell, for example, a memory cell of a stacked gate structure having a floating gate electrode, is determined by the quantity of electrons in the floating gate electrode. Also, the quantity of electrons in the floating gate electrode is controlled, for example, by applying an F-N tunnel current to a tunnel insulating film.
2.1. Circuit Configuration
FIG. 1 shows a conventional read circuit of a NOR cell type flash memory.
This read circuit has a so-called double-ended type which compares a current Iref flowing into a reference cell with a current flowing into a selected memory cell to determine data in the memory cell (“1” or “0”).
S/Ai indicates one sense amplifier. Generally, a plurality of sense amplifiers are disposed in a memory chip. Also, a plurality of bit lines BL1, . . . , BLn are connected to a single sense amplifier S/Ai through a column gate. Further, a read control signal generating circuit is connected to the sense amplifier S/Ai, and provides a read control signal to the sense amplifier S/Ai upon reading. The read control signal generating circuit includes a reference cell.
Then, upon reading, the cell current Iref of the reference cell is set to be substantially equal to a cell current Icell flowing into a memory cell which stores “1” data (“1”-programming cell). In other words, assuming that the memory cell is identical in structure to the reference cell, the reference cell is set to “1”-programming state (negative threshold voltage state).
As a read potential (ground potential) is provided to a selected word line and a dummy word line, and the cell current Iref flows through the reference cell, a current flowing into an RSA node 33 (RBL) is set to Iref/2 (=Icell/2) by current mirror circuits MR1, MR2. Reference letter W represents the size of a transistor (channel width).
When a selected memory cell stores “1” data (in the case of “1”-programming cell), Icell flows into an SA node 33 (BL), so that the potential at the SA node 33 becomes lower than the potential at the RSA node 33.
On the other hand, when a selected memory cell stores “0” data (in the case of “0”-programming cell), little current flows into the SA node 33 (BL), so that the potential at the SA node 33 becomes higher than the potential at the RSA node 33.
Therefore, data in a selected memory cell (“1” or “0”) can be discriminated by detecting a potential difference between the SA node 33 and the RSA node 33 using a differential amplifier DA.
2.2. Consumed Current During Read
In the NOR cell type flash memory, when the read circuit as described above is used, for example, it can be thought that a consumed current during a read mainly consists of the following three currents:                cell current: Icell        current produced by the differential amplifier: Iamp        current produced in components other than the above: Ielse        
A majority of Ielse is occupied by a current consumed by an intermediate potential generating circuit required for a read operation.
Consider now that a read is performed in units of 16 bits (=1 word).
In this event, since 16 sets of read circuits are required, a total value Itot of consumed currents during the read is calculated as:       I    tot    =            16      ×              (                                            3              2                        ⁢                          I              cell                                +                      I            amp                          )              +          I      else      
In the equation (1), a factor 3/2 in the first term of the right side is based on the sum of a cell current Icell of a memory cell which stores “1” data (“1”-programming cell) and a cell current Iref/2 of the reference cell (=Icell/2).
For reducing the value Itot, the value Icell or Iamp in the first term of the right side, or the value Ielse in the second term of the right side may be reduced. However, the first term on the right side exerts a larger influence on Itot than the second term on the right side does. For this reason, whatever expedient is adopted for reducing the second term on the right side, i.e., the value Ielse, the resulting effect on the reduction in Itot is not so large.
Therefore, it can be understood that a reduction in the value of the first term on the right side is effective for reducing the value Itot. However, it is quite difficult to reduce the value Icell in the first term on the right side. This is because if Icell is simply reduced alone without changing a method of sensing a potential on a bit line (read data) during a read, a read time is necessarily extended.
Thus, for reducing the value Itot, it is only Iamp that leaves ground for consideration.
However, the value Iamp depends on a time required by a differential amplifier for amplification (=sense time). Specifically, in the read circuit of FIG. 1, for example, a significantly large current need be consumed for amplifying the potential difference between the SA node 33 and the RSA node 33 at a high speed. Assuming that Icell is set to approximately 30 μA and a sense time to approximately 30 nsec, Iamp is required to be as large as 50 μA or so.
In other words, since the sense time and the consumed current are in a trade-off relationship in a read operation, the conventional read circuit is disadvantageous in that a faster read operation and lower power consumption cannot be simultaneously accomplished.
As appreciated, the read circuit of the conventional nonvolatile semiconductor memory, for example, a read circuit of a NOR cell type flash memory is disadvantageous in that a faster read operation and lower power consumption cannot be simultaneously accomplished.
Also, for nonvolatile semiconductor memories other than the NOR cell type flash memory, the faster read operation and lower power consumption are critical problems. For example, the read circuit of the NOR cell type flash memory can be applied as it is as a read circuit of the aforementioned 3Tr-NAND. In this case, the faster read operation and lower power consumption must be accomplished in the 3Tr-NAND as well.
Particularly, since the 3Tr-NAND has been developed for use in portable devices with low power consumption such as a non-contact type IC card, the faster read operation and lower power consumption are extremely critical.